Sign In
Get Clay Free →

Suggestions

    Jayaprakash Hk

    Design and Verification Engineer at TCS

    Jayaprakash HK is a highly experienced professional with over 7 years of work experience in FPGA/ASIC Front-end assignments.

    His expertise lies in Design & Verification, focusing on Design Architecture, RTL Coding, FPGA Validation, and FPGA/ASIC Verification.

    He is proficient in CFP MSA Standards, ARM Based protocols AMBA APB, AXI, and Communication Protocols like MDIO, PCIe, OBSAI RP1, UART, SPI, I2C, ARINC-429.

    His work spans across Telecom, Automotive, and Aerospace industries, with additional experience in IP Core development assignments.

    Jayaprakash has extensive knowledge of HDLs/programming languages such as Verilog, VHDL, System Verilog, TCL, and Python.

    He has exposure to EDA Tools including Altera Quartus, Xilinx ISE, ModelSim, and Cadence NCSim.

    Jayaprakash HK pursued his BE in Telecommunications at Dr. AIT Bangalore and his M.Tech in VLSI / Embedded Systems at R. V. College of Engineering, Bangalore.

    He has worked as a Design and Verification Engineer at TCS and as a Trainee Engineer at MindTree.

    Jayaprakash Hk
    Add to my network

    Location

    Bengaluru, Karnataka, India