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    Mehran Amrbar

    Lead FPGA Designer at NASA Jet Propulsion Laboratory

    Mehran Amrbar is an Engineering Manager at NASA Jet Propulsion Laboratory (JPL) with extensive experience in electrical engineering and FPGA design.147 He has over 10 years of hands-on experience with VHDL and Verilog.1 Amrbar's career at JPL has progressed from Lead FPGA Designer to his current role as Engineering Manager.26

    Education and Expertise

    Amrbar holds a degree from California State University-Northridge.1 His expertise includes:

    • ASIC design with a focus on low power methodology5
    • Single Event Effects measurements on FPGAs, particularly the Xilinx Zynq-70008

    Recent Developments

    As of November 13, 2024, Amrbar shared news about layoffs at JPL in La Cañada Flintridge, indicating his continued involvement with the organization's affairs.6

    Amrbar is also an advocate for diversity in STEM fields, having posted about women in leadership and women in STEM on his LinkedIn profile.3

    Highlights

    May 22 · seemapld.org
    [PDF] Analysis of the Single Event Upsets in the Programmable Logic of ...

    Related Questions

    What projects has Mehran Amrbar worked on at NASA Jet Propulsion Laboratory?
    How did Mehran Amrbar transition from being a Lead FPGA Designer to an Engineering Manager?
    What are some notable achievements of Mehran Amrbar in the field of FPGA design?
    Can you provide more details about Mehran Amrbar's educational background?
    What challenges has Mehran Amrbar faced in his career at NASA Jet Propulsion Laboratory?
    Mehran Amrbar
    Mehran Amrbar, photo 1
    Mehran Amrbar, photo 2
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    Location

    Greater Los Angeles Area