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Yokesh Ramasamy
Design Verification Engineer at Cirrus Logic
Professional Background
Yokesh Ramasamy is a distinguished engineer specializing in ASIC verification, validation, and design with over six years of robust experience in the semiconductor industry. Currently positioned as a Design Verification Engineer at Cirrus Logic, Yokesh has developed a comprehensive skill set that includes proficiency in multiple programming languages such as UVM, System Verilog, and Python. His hands-on experience with complex Radar Signal Processing systems stands out in his career journey, marked by significant contributions to innovative technology projects.
Before joining Cirrus Logic, Yokesh honed his expertise in various significant roles. He served as a Staff Engineer at Uhnder, Inc., where he expanded his capabilities in engineering design and verification processes. His previous tenure at Juniper Networks and Quality Assurance at Qualcomm allowed him to master complex verification methodologies and successfully manage integrated circuits' design workflows. His early professional experiences were shaped by his roles at Analog Devices, MindTree, and HCL Technologies, where he laid the foundational knowledge and skills necessary to thrive in this competitive field.
Throughout his career, Yokesh has been involved in numerous projects that showcase his versatility and technical prowess. From validating Bluetooth EDR on FPGA platforms to verifying intricate radar signal processing pipelines, he has consistently delivered high-quality results that align with industry standards. This dedication reflects his commitment to excellence in ASIC development and validation, contributing positively to the companies he has collaborated with.
Education and Achievements
Yokesh Ramasamy's academic journey began with a Bachelor of Engineering in Electronics and Communication (ECE) from PSG College of Technology, where he achieved an outstanding 9.18 GPA. His thirst for knowledge led him to pursue further studies in Electrical Engineering with a focus on VLSI at the esteemed University of Minnesota-Twin Cities, graduating with an impressive GPA of 3.85. This strong educational foundation has set the stage for his professional advancements in the field of ASIC design and verification.
During his academic pursuit, Yokesh actively engaged in various graduate projects that equipped him with hands-on experience in VLSI design and verification. Noteworthy projects included the design and layout of a 128KB SRAM using HSPICE and the implementation of ATPG test data compression through Viterbi algorithms. These projects not only refined his technical expertise but also demonstrated his capability to tackle complex challenges in digital design, setting him apart from his peers.
Yokesh's career achievements are further highlighted by his notable projects at Cirrus Logic and previous organizations. He has effectively led a range of initiatives, including the verification of complete radar signal processing digital pipelines and the development of coverage closure strategies for complex designs. His work in post-silicon bring-up of futuristic radar SoCs aligns with ongoing advancements in defense and automotive applications. His expertise in UVM_REG and System Verilog has contributed to successful project deliveries across various platforms, showcasing his ability to adapt and innovate in fast-paced environments.
Achievements
Yokesh Ramasamy boasts an impressive portfolio of projects that stand as a testament to his dedication and skill in the field of Electronics and Communication Engineering. At Cirrus Logic, he was integral to verifying various components of radar signal processing systems, which involved comprehensive validation strategies and effective use of simulation tools. Some significant projects include:
- Verification of SPMI Interface: This project encompassed the rigorous examination and validation of the Serial Peripheral Memory Interface protocol, ensuring high reliability and performance in communication for semiconductor devices.
- Verification of Complete Radar Signal Processing Digital Pipeline: Leading this project demonstrated Yokesh's advanced understanding of radar technology and his ability to integrate complex digital circuits for superior functionality.
- Post Silicon Bring-up of Futuristic Radar SoC: Through this role, he contributed to the practical deployment of next-gen radar systems, validating that they perform as expected in real-world scenarios.
- Design and Modeling of Synthesizable Channel Model for Palladium Validation: This experience underscores his innovative approach to channel modeling, vital for optimizing system performance.
- Development of Verification Regression Script: His efforts in developing comprehensive regression scripts have streamlined the verification process, increasing efficiency and reliability in testing methodologies.
In previous roles, he has also made notable contributions to diverse projects involving Bluetooth EDR on FPGA and the validation of Ethernet PHY layers, underscoring his varied technical expertise. Additionally, his work on Viterbi Decoder modeling and performance evaluations exemplifies his concentration on optimizing algorithmic performance in hardware designs. Yokesh's commitment to quality and innovation in ASIC verification is commendable and positions him as a leading professional in this field.