Arsen Julhakyan

Arsen Julhakyan is a highly skilled professional with a deep knowledge of VHDL, Verilog hardware description languages, and logic design. He possesses expertise in System Verilog language, UVM verification environment, and various scripting languages such as Makefile, Perl, Python, Tcl, and Cshell.

Arsen has extensive experience in multi/single-core embedded programming using Real-Time Operating Systems and languages like Assembly, C, and C++. He is well-versed in utilizing tools such as Cadence Incisive Simulator, Synopsys VCS, Mentor Graphics ModelSim, Xilinx ISE, Altera Quartus II, Synopsys Design Compiler, and Prime Time, among others, for digital hardware simulation, synthesis, and power optimization.

Additionally, Arsen is competent in revision control systems like Perforce (p4), SVN, and CVS. He has been introduced to SystemC and VHPI interface and is proficient in AMBA protocols such as APB, AHB, AHB Lite, and AXI.

His specialties include RTL (VHDL, Verilog) Design, System Verilog, UVM verification, FPGA, ASIC, and Embedded Programming.

Arsen pursued his MSc in System on Chip Design from Kungliga Tekniska högskolan and holds a Diplomated Specialist degree in Industrial Electronics from Hayastani Petakan Chartaragitakan Hamalsaran.

Arsen Julhakyan currently serves as the CTO at Altered Silicon, Inc. He has previously worked in various roles including as the CTO at HashMax, a Senior Engineer at ARM, Design and Verification Engineer at ARM, Hardware Design Engineer at Imagination Technologies, Graduate Design Engineer at Imagination Technologies, Junior Digital Designer at Melexis, and Intern at ARM.