Brent Lui

Brent Lui is a seasoned CPU & ASIC professional with two decades of experience in ASIC and CPU chip design, specializing in design verification, architecture verification, and CPU pipeline design.

His expertise includes various facets of ASIC and CPU design such as test plan development, test bench creation, test case development, assembly tests, compatibility tests, random tests, gate-level simulation, regression testing, coverage analysis, RTL design, RTL synthesis, timing verification, post-layout debug, power analysis, and LEC with tools like Cadence Conformal.

Brent has a strong background in Superscaler and superpipe ARM CPU design verification, DDR design verification, and intricate ASIC design like G-bit Ethernet and CPU subsystem design.

He has vast experience in ASIC design flow and has worked with different CPU architectures such as ARM, x86, and MIPS. Additionally, Brent has been involved in the complete development cycles of complex Networking ASIC designs like G-bit Ethernet, MCNS cable modem client, Media Gateway, and TCAM.

Brent Lui holds a Master's degree in Computer Engineering from Syracuse University and a Bachelor's degree in Electronic Engineering from National Chiao Tung University.

His professional journey includes roles like staff logic verification engineer and logic design engineer at Marvell Semiconductor, Senior Staff Design Engineer at Broadcom, Senior ASIC design engineer at EmpowerTel Networks Inc, 3Com, Sony Electronics, LSI Research Lab, AMD, and Design Engineer at Intel Corporation.