Jules Bassale

Jules Bassale is a seasoned ASIC/FPGA Verification Engineer who is passionate about continuous learning and staying at the forefront of innovation. With expertise in Verilog, System Verilog, UVM, RTL design, timing closure, and formal verification, Jules has honed a versatile skill set in the field of hardware design. Jules holds a Master's degree in Statistics and a Bachelor of Science in Computer Engineering, both earned from Portland State University. Currently, Jules serves as a Design Verification Engineer at Apple, bringing valuable experience and knowledge to the technological powerhouse.