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    Vineet Nayak

    Design Verification Engineer at Qualcomm

    Vineet Nayak is a highly skilled professional interested in Frontend ASIC/RTL/SOC Design and Verification roles, with expertise in System Verilog, Perl, C, Assembly, and UVM. Vineet has a strong educational background, including a Master's degree in Electrical Engineering with a GPA of 4.14/4.0 from the Ira A. Fulton Schools of Engineering at Arizona State University, and a Bachelor of Technology in Electrical Engineering with a GPA of 8.46/10.0 from the College of Engineering and Technology, Bhubaneswar.

    In terms of work experience, Vineet has held the position of Senior Design Verification Engineer at Qualcomm and previously worked as a Design Verification Engineer at the same company. Vineet has also worked as a Digital Design Intern at NXP Semiconductors, Student Tutor at Ira A. Fulton Schools of Engineering at Arizona State University, Assistant Manager at Maruti Suzuki India Limited, and Graduate Engineer Trainee at Maruti Suzuki India Limited.

    Vineet Nayak
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    Location

    San Diego, California, United States