Saurabh Ahuja

Saurabh Ahuja is a highly skilled verification engineer with a strong background in Universal Verification Methodology (UVM) and a focus on verifying IP blocks for functionality and toggle coverage matrix.

He has developed verification components such as monitors, drivers, scoreboard, UVM sequences, and test cases to thoroughly verify designs, particularly related to protocols like PCI-Express.

Saurabh has ported C++ test benches to system verilog, enhancing efficiency in design verification.

He is adept at creating and debugging test cases, collaborating with designers on failing scenarios, and assisting SOC teams during integration and initial bring-up phases.

Previously, Saurabh worked on verifying Debug clients, DDR Interface, Corenet System Interconnect Interface, demonstrating a diverse range of expertise.

In terms of project experience, Saurabh has contributed to the design and verification of DMA Client-based systems, focusing on synthesizable System Verilog constructs, constraint-based randomization techniques, and achieving 86% functional coverage.

He was also part of a team that designed a Parallel to Serial Interface (PSI) and a Look Through Cache memory subsystem, showcasing his ability to work collaboratively and lead small teams effectively.

Saurabh's specialties include Hardware Description Languages (Verilog, VHDL, System Verilog), Programming Languages (C, HTML, SQL, DB2, PERL, TCL, MATLAB), and various Engineering Tools and packages like Xilinx ISE, L Edit, Synopsys VCS, ModelSim, PSpice, and MS Office 2007.

He pursued a Bachelor of Technology (BTech) in Electrical and Electronics Engineering from the College of Engineering Roorkee, followed by a Master of Science (MS) in Electrical and Electronics Engineering from California State University-Sacramento.

Saurabh has held positions at reputable organizations such as AMD as a Member of Technical Staff, Amazon as a DV Engineer, Trend Micro as an Electrical/Hardware Engineer VI, and Freescale Semiconductor in SOC IP Verification and IP Verification Engineering roles.

His professional journey also includes roles at Infosys Technologies Ltd as a Software Engineer and internships at Bharat Heavy Electrical Ltd Haridwar and California State University, Sacramento.