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    Lev Vaskevich

    VLSI Design and Architecture expert

    Lev Vaskevich is a seasoned professional with 13 years of experience in VLSI design, architecture, and verification. His expertise includes VLSI architectural research, design and implementation, verification using System Verilog UVM, and defining project methodologies. Lev has served as a Team Leader and uArchitect for Marvell's packet scheduler and has been instrumental in VLSI architecture and design for Marvell's next-generation Switch, Packet Processing Multi-Core subsystem, and Programmable Network Subsystem. He has also contributed to VLSI design and verification for the B4680 Basestation on Chip and played a key role in the VLSI architecture research and design for the SC3900 Digital Signals Processor project, as well as in the VLSI design of Control units for the SC3850 Digital Signal Processor project.

    Lev Vaskevich
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    Location

    Israel