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    Venkatesh Patil

    Digital IC Track Director, Asst. Prof of Practice PSU-ECE, X-Engineering Director, Numascale | X-Intel, X-Rockley Photonics | ASIC | SOC | HPC | AI | ML

    Venkatesh Patil, a semiconductor professional with 20 years of experience, is known for his leadership, problem-solving, and program management skills. He has delivered 20+ chips from concept to silicon and has hands-on experience with new technologies, tools, flows, and methodologies. Venkatesh is an expert in RTL to GDSII timing closure, using industry-standard EDA tools such as Synopsys and Cadence, on various design architectures, and using deep sub-micron process nodes from TSMC, AVAGO, Intel foundry vendors. He is highly effective in spearheading programs, harnessing leading technologies, hiring multi-disciplinary global teams, and delivering semiconductor solutions. In addition to his technical expertise, Venkatesh is a data enthusiast and a learner with a focus on learning the technologies in Machine Learning (ML)/ Deep Learning (DL)/ Artificial Intelligence (AI) and its application in Healthcare and Automotive Industries. He is also passionate about teaching, mentoring, and helping youths create joy for learning.

    Highlights

    Jun 23 · dac.com
    [PDF] the chips - Design Automation Conference

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    Venkatesh Patil
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    Location

    Portland, Oregon, United States