University of Minnesota

National Institute of Technology, Tiruchirappalli

Server Systems Performance Architect at AMD

Server systems performance architect working on systems characterization, performance and competitive analysis

Senior Member Of Technical Staff

I was part of the Processor Architecture Research Lab at Intel, Bangalore conducting research on  techniques to improve the front-end performance of modern super-scalar processors

Intel Corporation

Research Scientist

I was part of the binary translation team working on a HW/SW co-design project.

Binary Translation Software Engineer

I worked with the Binary Translation team investigating security applications of binary translation. My work explored using binary translation as a solution for jump-oriented programming (JOP) malware attacks. As part of this work I reverse engineered multiple windows applications to learn their code behavior. I modified the binary translation software to identify valid targets of indirect jump instructions in the binary using both static binary information as well as dynamic information gathered at run-time.

Graduate Research Intern

My internship work involved optimizing the memory performance of multi-threaded workloads on Intel's server processors. I extended the existing cache dead block predictor algorithm to handle simultaneous multi-threading. I explored the design of a sharing-aware last-level cache dead block predictor scheme for server workloads. As part of this work I conducted a detailed  characterization study of the applications and proposed a novel dead block predictor scheme to improve their performance. I had a chance to work with Intel's in-house architecture simulator. The work resulted in a patent.

My research dealt with various aspects of the memory characteristics of multi-threaded applications. In particular, I studied problems related to the performance and correctness issues of multi-threaded applications running on multi-core processors. As part of my research I explored the correctness issues during cross-ISA emulation of multi-threaded applications on multi-core processors. I worked on designing sharing-aware cache replacement policies for multi-threaded programs. I also worked on characterizing the performance of emerging multi-threaded workloads, and the effect of compiler optimizations on such programs. I have had a chance to work with a wide range of tools and simulators as part of my research.

Ragavendra Natarajan