Peter Andriukaitis

Peter Andriukaitis is a professional with expertise in designing various functional blocks for high-speed network security accelerating FPGAs. His work includes developing PCS and MAC layers for multi-lane high-speed serial links like Interlaken and 40G XLAUI Ethernet using Altera and Xilinx transceivers, as well as creating device-initiated AXI/PCI DMA transfer logic for Amazon F1 AWS. He also specializes in custom pattern search and machine learning logic, interfacing with vendor-provided IP modules, and working on DDR3/DDR4, QDR-II SRAM, Regex Processor, and PCI Express technologies.