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    ParthaSarathy Gopal

    Director Digital EDA and IP at MaxLinear

    ParthaSarathy Gopal is an accomplished executive with a strong focus on quality and efficiency in the ASIC design sector, specifically in Deep submicron and the latest finfet technologies such as 5nm designs.

    With extensive experience in foundation IP, including standard cells, memory compilers, GPIO, serdes, and synthesizable IP like CPUs and interface controllers, ParthaSarathy excels in strategic planning, business development, and establishing valuable partnerships with CAD and IP vendors.

    His specialties lie in chip design foundation IP, CAD & IP vendor relationships, strategic technology partnerships, and IP/license contract negotiations. Additionally, he is known for his analytical-driven, consultative management style that emphasizes hiring, development, and motivation of team members.

    Having served in key roles at reputable companies such as MaxLinear, GLOBALFOUNDRIES, Qualcomm, and Conexant, ParthaSarathy has a robust educational background with a Bachelor's in Electrical and Electronics Engineering, a Master's in Electrical Engineering with a focus on Microelectronics, and an MBA in Management.

    He has played pivotal roles including IP development management, leading teams in IP creation and third-party IP acquisitions, offshore IP team development and deployment, as well as designing and implementing IP development processes and flows.

    ParthaSarathy Gopal's leadership and technical expertise have been instrumental in driving innovation and optimizing efficiencies within the ASIC design industry.

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    Location

    San Diego, California
    Location