Oz Tal

Oz Tal is a seasoned professional with a strong background in RTL to GDS full flow implementation, including synthesis, Place & Route processes.

With expertise in Static Timing Analysis (STA), Oz has hands-on experience in both block and full chip levels, ensuring implementation and Sign-off flows are meticulously executed.

Proficient in developing and supporting various flows and scripts, Oz is well-versed in DFT/ATPG and Formality, enhancing the efficiency of projects.

As a team player with a proactive attitude, Oz Tal is known for being a quick learner, highly motivated, and committed to delivering exceptional results.

Having worked with a range of Synopsys tools such as Design compiler, ICC, ICC2, Primetime-SI, Formal Verification, and Lynx-TSL, Oz has a comprehensive understanding of the design process.

Oz's proficiency in scripting languages like Perl and TCL further amplifies his capabilities in streamlining tasks and improving productivity.

Oz Tal earned an Engineer's Degree in Electrical and Electronics Engineering from Technion - Israel Institute of Technology, solidifying his academic foundation in the field.

With a rich professional history, Oz has previously held significant roles as a Staff Backend Engineer at NVIDIA, a Senior Backend Engineer at Mellanox Technologies, and a Senior Backend Engineer at EZchip, showcasing his expertise and experience in the industry.