Neelima Chennamaneni

Neelima Chennamaneni is an experienced Design Verification Lead with over 11 years of expertise in Memory Controller IPs for DDR4/DDR5/LPDDR4/5/HBM DRAM arrays and Graphics (GPU) processor design units.

She is skilled in architecting intricate testbenches in UVM, creating reusable verification IPs, bus-functional models, reference models, and DV infrastructure. Neelima has led DV teams, managing all phases from testplan creation to System Verilog UVM testbench development, verification reviews, and power aware simulations.

Neelima Chennamaneni is proficient in Gate Level Simulations and supporting validation and software teams during early bring up phases. She excels in collaborating with global engineering teams, ensuring the delivery of high-quality results to meet project objectives. Neelima has a background in developing project schedules and adeptly resolving resource conflicts.

She holds a Master's degree in Electrical, Electronics, and Communications Engineering from the University of Massachusetts, Amherst, and a Bachelor's degree in Electrical and Electronics Engineering from Birla Institute of Technology & Science, Pilani.

Neelima has held significant roles in reputable organizations, including Senior SoC Verification Engineer at Microsoft, Staff Design Verification Lead, and Senior SoC Design/Verification Engineer at Intel Corporation, as well as Pre-Silicon Verification Engineer at Intel Corporation.