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Kuldeep Singh
Manager, Backend Physical Verification, Chip Finishing and Tapeout Sign-off
Professional Background
Kuldeep Singh is a seasoned professional boasting over 9 years of management experience in the semiconductor industry, particularly in the realm of Physical Verification and CAD tools. He has played a pivotal role in shaping teams that deliver robust solutions and innovative methodologies tailored for the Physical Verification, Chip Finishing, Design for Manufacturability (DFM), and sign-off processes associated with Sun/Oracle's SPARC Microprocessors. Kuldeep has consistently demonstrated his expertise by adeptly guiding teams through a diverse array of challenges, including the rollout of Foundry Rule checks and the development of in-house Chip Finishing rule checks featuring advanced CAD flows.
Throughout his illustrious career, Kuldeep has overseen the successful tapeout sign-off of SPARC Processors, specifically within the M series designed at key process nodes of 90nm, 65nm, 28nm, and 20nm. His unique insight into the limitations posed by reticle size in these advanced nodes has allowed him to navigate complex technical challenges effectively.
Kuldeep's extensive experience includes a proven track record of managing teams responsible for Physical Verification (PV) rule checks and CAD tool evaluation. His leadership resulted in the sign-off of 9 SPARC Processors using TSMC processes from 40nm down to 20nm between 2008 and 2016. Prior to that, from 2002 to 2008, he served as the Lead Physical Verification Engineer, implementing rule checks for sign-offs and Chip Finishing for 5 SPARC Processors at the 90nm to 45nm TI process, underlining his depth of experience in the field.
Education and Achievements
Kuldeep Singh's educational background includes a Master's degree in Science from Clemson University, complemented by a Bachelor's degree from Osmania University. This solid academic foundation has equipped him with the necessary knowledge and skills to excel in the semiconductor domain.
Kuldeep's contributions to the field have been recognized through various accolades, including the granting of 2 US patents in the back-end design domain, showcasing his innovative mindset and technical prowess. His technical skills span the development of best practices in Physical Design Verification, demonstrated through the creation of pioneering rule checks in Mentor Graphics Calibre for critical process nodes, such as Redundant Via Checks, Rule-Based DRC Waiver Flow, Equation-Based Antenna Checks, Unit Dummy Fill Flow, and LVS Finger Checks.
His collaborative spirit is evident through his participation as a member of the DAC Designer Track Technical Program Committee from 2015 to 2016, where he contributed valuable insights to advance the industry's knowledge base. Kuldeep has also shared his expertise as a presenter at esteemed conferences such as DAC and the Mentor Graphics User Group Conference.
Notable Achievements
- Proven Leadership: Recognized as a proactive leader in nurturing and mentoring teams, Kuldeep has successfully overseen the sign-off of more than 10 SPARC chips, signifying his ability to inspire and lead others to achieve excellence in the face of technical challenges.
- Intellectual Contributions: Kuldeep’s two US patents highlight his role as an innovator in back-end design, reflecting his dedication to pushing the boundaries of semiconductor technology.
- Community Involvement: His engagement with the DAC Designer Track Technical Program Committee and conference presentations illustrates his commitment to fostering collaboration and knowledge-sharing within the semiconductor engineering community.
- Technical Excellence: With extensive expertise in using Mentor Graphics Calibre for Physical Design Verification and proficiency in the Cadence Virtuoso platform for layout, Kuldeep continues to lead initiatives that optimize the physical design methodology in a rapidly evolving industry.
In summary, Kuldeep Singh emerges as a notable figure in the semiconductor industry, leveraging his extensive experience, technical skills, and innovative approach to drive successful outcomes across diverse projects. His commitment to collaboration, leadership, and continuous improvement has made a lasting impact on the SPARC Microprocessor family and the broader field of Physical Verification. He stands as a testament to the power of dedication and expertise in shaping the future of technology.