Texas Tech University

Senior Staff Performance Modeling Engineer at Zeku, inc

Skills: SystemC · C++ · Simulations · Lua · Synopsys Platform Architect · TLM · Embedded Systems · SoC

Leidos

Senior Staff Research Engineer 

ZEKU Technologies

Principal Performance Modeling Engineer

Zeku, inc

Senior Staff Performance Modeling Engineer

Cost account manager responsible for managing TLM branch tasks, planning, and earned value management.  Responsible for managing how closely to the planned schedule the groups work is tracking, and explaining any variance causes and corrective measures possible.

TLM Control Account Manager

Lead the effort in the modeling effort of complex SoC designs.  Help guide the direction design path of the designed chips through early simulations and help to find potential performance boosting trade offs.  Assist in achieving the eventual goal of becoming the government's primary supplier of custom SoC devices.

SoC Architect and Research Engineer

Create performance models for evaluation of architecture bottlenecks and possible improvements in  memory controller logic.
Updated, optimize, and add new features to existing models while maintaining cycle accurate behavior needed for performance validation.

Created new design flow using a pseudo-code to flow chart creation tool:  Enabled us to create pseudo-code of new features and models and have that information reflected in a dynamic updated flow chart.   This flow chart and pseudo-code can be used from the top level design and passed to the RTL level to ensure that modules all share in the same assumptions and design choices.

Qualcomm

Staff Engineer

SystemC modeling of switch structure architectures
Evaluation of trade offs in features vs performance in models
Created regression scripts to sweep all feature varying parameters
Created general use models to facilitate other team members to create new models quickly and reliably
Evaluated third party models for possible Huawei usage
Gained experience in AXI protocol and created AXI to switch bridges 
Performed simple top level model studies of questions that needed quick answering, like parallel networks vs singular networks with higher data rates/bus-widths. 
ESL modeling work done prior to RTL, which allowed my work to strongly influence the development of the RTL code

Huawei

Staff Engineer: Hardware modeling

Worked at TI for 5 years now.  Moved into Digital Verification using System Verilog to test devices for functional and code coverage. 

Tools used:  VCS Simulator, NCSim
Languages used:  System Verilog, perl, shell scripts

Texas Instruments

Digital Verification Engineer

Wrote models to test system architecture performance for abstract transfers.  Worked with full SoC designs.

Languages:  SystemC, C++, perl

John C.