Hitesh Oswal

Hitesh Oswal is a skilled professional with over 3 years of experience in digital design, debugging, and testing hardware prototypes in cutting-edge technologies at Axiado Corporation. He specializes in RTL languages like Verilog, SystemVerilog, CHISEL, and possesses hands-on experience in ASIC design flow.

During his tenure, Hitesh has honed his expertise in digital logic design, debugging, clock domain crossing, functional verification, synthesis, floorplanning, static timing analysis, and FPGA prototyping. His proficiency extends to programming languages such as Verilog, SystemVerilog, VHDL, CHISEL, TCL, Bash, Python3, C, and RISC-V Assembly.

He is adept at utilizing tools including Synopsys VCS, Xilinx Vivado, MATLAB, oscilloscopes, logic analyzers, FPGAs, function generators, and DMM. Hitesh is well-versed in on-chip bus protocols like AXI, APB, AHB, Wishbone, and TileLink, and excels in debugging and resolving complex technical issues.

Hitesh holds a Bachelor of Engineering (BEng) in Electrical, Electronics, and Communications Engineering from KIT's College of Engineering, Kolhapur, and a Master's Degree in Computer Engineering from California State University-Chico. With a background that includes roles at NVIDIA, Axiado Corporation, Scalable Systems Research Labs Inc., and academic positions at California State University, Chico, Hitesh has demonstrated his expertise in the field of digital design and verification.

Reach out to explore Hitesh's insights and experiences in design and verification for innovative projects.