David Chen

David Chen is a veteran in the semiconductor and silicon IP industries with over 30 years of experience.

He significantly contributed to the IEEE 754™-2019 Standard for Floating-Point Arithmetic by identifying a non-associativity erratum in the IEEE Std 754™-2008, proposing a solution that was unanimously accepted.

David's expertise led him to become a voting member of the IEEE P3109 committee, focused on establishing data format standards crucial for Machine Learning technologies.

In 2020, David founded Arith, a research venture specializing in computer arithmetic and semiconductor IP development, securing a federal grant from the NSF to further innovations.

Arith's current focus is on developing an AI Chip Accelerator based on compact floating-point formats aligned with the upcoming IEEE 3109 standard, with the goal of democratizing AI technology for broader accessibility.

His tenure at Cadence®/Tensilica® showcased his leadership abilities, notably contributing to the creation of the Cadence®/Tensilica® floating-point units (FPU) and inventing a patented Fused-Multiply-Add (FMA) IP, emphasizing efficiency and high performance.

David's educational background includes a BS in Computer Science and an MS in Computer Engineering from Santa Clara University.

Throughout his career, David held various leadership roles in renowned organizations such as Arith Inc., AlayaTec, Cadence Design Systems, Tensilica, and more, demonstrating a diverse skill set in engineering and technology advisory roles.