Montana State University-Bozeman

North Dakota State College of Science

Staff Electrical Engineer at Syncroness

Loveland, Colorado

Syncroness

Staff Electrical Engineer

- Lead HW architecture and design of a scalable Data Accelerator and enterprise level NVMe SSD products. •	Both designs utilized RISC-V processor cores, Network on Chip (NoC) IP, DDR, ONFI and Toggle NAND interfaces. •	Products also incorporated Advanced Encryption Standard (AES), RSA, Secure Hash Algorithm (SHA), Elliptical Curve Coding, as well as data compression/decompression, Encryption key management/generation, key exchange, and secure key storage.

Goke US Research Labs

HW Architect

Developed architecture for measuring various video compression algorithms.

FLXSA, LLC

FW Architect / Designer

Remotely designed and implemented, in an FPGA environment, a performance measurement module required for a PCIe-to-Ethernet Network SOC.

Kazan Networks

SR. ASIC Designer

Technical/Design lead for scalable SAS/SATA/PCIe SSD's.. Responsibilities include HW Design architecture, interface requirement development, RTL design, FW integration and training, as well as test, verification, and validation.

Micron Technology

Principle Architect / ASIC Designer

Developed LSI’s SATA/SAS IP cores from concept through implementation into successful multi-customer ASIC programs.

LSI, an Avago Technologies Company

Sr. IP Design Engineer

Lead HW effort for the US Air Force F15E Digital Map System. Responsibilities included HW Architecture and testing. Management, scheduling and leadership role for 5 designers. Monitor design status, conduct hardware design reviews, correlating testing and firmware integration of the Digital Map System.

Honeywell Defense Avionics Systems

HW Design Project Lead

Instrument Engineer -Duties included the maintenance and calibration of seismic data computers, and other electrical components in remote desert sites. Supervised a crew of 90 individuals, many of whom could not speak English

Steve Schauer

Steve Schauer