University of Hawaii at Manoa

Skills: FPGA · Computational Photography · Strategic Development · Team Management · Large Projects · Cost Reduction · Device Drivers · Executive Management · People Management · Firmware · Engineering Leadership · Computer Science · Entrepreneurship · Design Thinking · Project Oversight · Debugging · Strategic Planning · Technical Standards · ASIC · Embedded Software · Design Engineering · Pitch Development · Communication · Big-Picture Thinking · International Management · Multi-site Team Management · Collaborative Leadership

Technology Consultant

Company sought to develop and deploy a secure digital content distribution system for the home entertainment market.  System architecture provided a technical solution to securely deliver high-definition movies to consumers, on demand.  System definition complied with FIPS 140-2 (level 3/4) requirements for secure information processing.  Business structure provided high royalty payments to content owners, while providing consumers with a broad array of content from recent releases to niche genres.  The product was also targeted as a market driver for other HD-related electronics systems, such as HD screens and HD cable boxes.  

We were a bit too early!

TitleWave, Inc.

Founder, President

Company developed a core MPLS switch with high port density and low overall power consumption per port.  System was built to meet all relevant NEBS requirements for central office Telecom equipment. 

Founded the company and helped secure A and B round funding.  Managed an engineering team of about 90 employees and 10 contractors.

Bravara Communications

CTO and VP of Engineering

Defined system backplane interconnect strategy based on detailed signal integrity analysis.  Defined next generation interconnect strategy, including box-to-box connectivity. 

Also assisted in the development of certain system FPGAs and system level verification strategy incorporating fabric ASIC, FPGAs and other major system components.

BrightLink

Circuit and Systems Architect

Developed texture map cache architecture for next generation product and led engineering team through implementation and debug of C model and Verilog RTL synthesis model.  Worked closely with performance analysis team to optimize overall system performance.  Filed two patents on the caching system.

3Dfx

Staff Engineer / Team Lead

Advanced Technology Group (ATG):  
Developed differential I/O pads, high-speed PLL/SerDes and built-in bit error rate instrumentation using standard CMOS technology as a proof of concept for IEEE 1596 standards effort.  Later worked on 3D graphics hardware accelerators using scan line and 2D variant techniques.  Filed a seminal texture caching patent in this area.

Apple Newton Group:
Developed one of the system ASICs used in Newton Message Pad 110/120 products.  Also developed low power design techniques and power analysis tools for performing dynamic power profiling for ASICs.

Bill Rivard