The University of Texas at San Antonio

University of Nevada-Las Vegas

Sr. Hardware Design Engineer

Apple

Sr. Hardware Design Engineer 

Senior Hardware Design/Validation Engineer  

•	Captured schematics of analog/digital designs for platforms applications, implemented PCB 
	designs layout, generated bill of material, purchased design components. Components search and      
       validation in the designs increased saving time and effort in new designs.
•	Prepared/studied board layout include stack up, routing topology, impedance, SI and PI simulation.
Prepared/executed plans for board bring up and platform testing. Created standardized platform layout design rules increasing speed in design processes cycle and assisted designer minimizing layout mistakes.
•	Coordinated with the SoC architectures/designers to get Silicon features and functionalities. Platform design cycle spanned 9 months, managed to design healthy system validation platform in 10 weeks, which saved time and thousands of dollars.
•	Designed add on boards for validation/debugging purpose. FPGA emulation platform assisted validation  
       team to catch hundreds of bugs before affecting design, resulting in more reliable healthy SoC free of  
       bugs.
•	Designed/Architected a full Platform automation system for remote access to test the new platform connectivity and functionalities the impact was saving the company’s time and hundred thousands of dollars for the company, and helped the manufacturing to speed up the production process.
•	Prepared and tested BKC for different purposes.
•	Prepared document release packages for the design and product includes hardware specifications.
•	Numerous design projects in mobile and server business group have gone into production and made millions of dollars for company success.
•	Created fabrication and assembly drawings and lab validation infrastructure, reused tools and equipment’s in lab and affected company bottom line revenues.

Intel

•	The main duty is designing motherboard; create symbols, footprints, driving new motherboard layout using CAD tools, and assembly, developing, qualifying, debugging, validating electronic designs of motherboards for new high end AMD CPU and GPU.

Motherboard Design Engineer (Contractor)

•	Design and capture schematics of analog/digital mixed-signal for fiber optics applications, implement PCB designs. Execute verification testing of prototypes and production samples. Designed a complete embedded thermal solution for SensorTran fiber optics products using C programming language on MCU Microcontroller.
•	Design and support testing for regulatory compliance (FCC, FM, etc). Solve problems during all phases, and support technical meetings and reviews.
•	Design layout of complex, high-density SMT, digital, and analog PCB’s using Cadense PCB designs (i.e. OrCad CIS, Allegro PCB LIBRARIAN, Allegro PCB Editor (Expert), Allegro SI (Spectra Quest SI), Allegro PCB router, Mentor Graphics.
•	Set Constraints based on layout guide.
•	PCB layout understanding with respect to the following technologies: Digital, HS Digital, Analog, RF, Mixed Signal Architectures, differential and single ended constraint.

SensorTran Inc.,

Hardware Design Engineer

•	Analog/Digital Hardware design/simulation of RAID controllers focusing on signal Integrity analysis of controller hardware to plan/implement stack-ups, power planes, decoupling, board setup, wiring constraints and board interface validation plans using Polar field solver, Cadence Allegro/Constraint Manager, HSPICE, Matlab, MathCAD, Logic Analyzer and Tektronix/Agilent 6/8/15/21GHZ Oscilloscopes. X86 Architecture knowledge along with high speed bus interfaces such as PCI-E, USB, FSB, IDE, Simulation consisted of driver/receiver model pairs for high speed SAS/PCI with Eye diagrams and DDR2 memory with 2D RLGC transmission line and via models. Worked on a card design project, the project includes IBM ASIC chip, SAS/SATA Interface, SCSI, PCI-X 266 Interface, 64 bit A\D bus width, DDR2, DDR3, PPC, Power distribution design, and Battery Backup charger. 
•	Recommended improved design changes for DDR2, SAS, PCI-E busses based lab validation/simulation results.
•	Completed board SI validation by checking signal integrity and timing of PCI, DDR2 memory, and SAS busses.
•	Prepared 8-16 layer boards for routing by implementing electrical, physical, and spacing constraints.
•	Created HSPICE driver/receiver simulations of transmission line effects using vendor IBIS and Hspice models.

AYMAN DODIN