Texas A&M University

National Institute of Technology, Tiruchirappalli

Research Scientist at Strategic CAD Labs, Intel Corporation

Hillsboro, Oregon, United States

- Addressing emerging challenges in HW / SW Co-validation- Leveraging pre-silicon knowledge for Electrical Validation- Property checking of large mixed-signal circuits- SMT based DC operating point analysis for large mixed-signal circuits

Intel Corporation

Research Scientist

Detection and diagnosis of out-of-specification failures in mixed-signal circuits- Fast failure probability estimation with empirical confidence bounds- Rule-induction based diagnosis of discovered out-of-specification failures- Identifying systematic shifts in pre-silicon belief with post-silicon dataAutomatic stability checking for large linear analog integrated circuits- Computationally efficient eigenvalue search for highly under-damped poles- Model order reduction based second order residue computation methods- Loop identification from second order node impedance functionsHybrid multi-algorithm parallel circuit simulation framework

Research Assistant

Custom layout design for IO interface devices

Parijat Mukherjee

Parijat Mukherjee