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Claris Leung
TD Module & Integration Yield Engineer at Intel Corporation
Claris Leung is a highly accomplished individual with a strong educational background and professional experience in the field of engineering. She pursued her Bachelor of Science (B.S.) at the University of California, Los Angeles, followed by further academic achievements with a Master of Science (MS) from Portland State University. Currently, Claris holds the position of TD Module & Integration Yield Engineer at Intel Corporation, where she leverages her expertise to contribute meaningfully to the company's success.
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Portland, Oregon Area
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Clay can make mistakes, so please verify responses. Data is from public sources. Trademarks are property of their respective owners.
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